发明名称 EXCLUSIVE LOGICAL OR CIRCUIT
摘要 PURPOSE:To obtain an exclusive OR circuit having a few number of employed transistors(TRs) and with less occupied area by constituting the circuit of the 1st and 2nd TRs of the 1st conduction type and the 3rd and 4th TRs of the 2nd conductor type. CONSTITUTION:A drain of a PNP TR11 is connected to an output node 18, the 1st logical signal input A is applied to the source and the 2nd logical signal input B is applied to the gate, respectively. Further, the drain of a PNP TR12 is connected to the output node 18, the input A is connected to the gate and the input B is connected to the source, respectively. Moreover, a drain of an NPN TR13 is connected to the output node 18, the input B is connected to the gate and a signal A' being an inverting signal of the input A is applied to the source, respectively. Further, the drain of an NPN TR14 is connected to the output node 18, the signal A' being the inverted A' is applied to the gate and the input B is applied to the source, respectively. Then, the exclusive OR circuit with a few number of employed elements and with small occupied area is obtained through the constitution above.
申请公布号 JPS59117827(A) 申请公布日期 1984.07.07
申请号 JP19820232927 申请日期 1982.12.24
申请人 TOSHIBA KK 发明人 KOIKE HIDEJI
分类号 H03K19/21 主分类号 H03K19/21
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