| 摘要 |
PURPOSE:To speed up a process time by shifting an address code signal with a decoded byte address signal and shifting and outputting the contents of the shifted number of the registers at every byte by every byte unit from a register file. CONSTITUTION:An address signal from a signal line 20 is decoded at a decoder 8 and is supplied to selectors 5, 6 and 7 and a register file 4 respectively, and based upon a byte address signal from a signal line 25, a select signal regarding a decode signal is made generate at a control circuit 9. And corresponding to the signal, it is selected whether the decode signal is outputted as it is or the one rotate-shifted by one bit to the right, and it is supplied to register files 1, 2 and 3, and outputs of byte unit from the files 1, 2 and 3 are shifted and outputted corresponding to the output of the selectors 5, 6 and 7 and the decoder 8 at a shifter 10. |
