| 摘要 |
An apparatus for decoding binary data from one form to another has a register adapted to receive the input bit signals. A plurality of data paths are connected to the register, with a delay means in at least one of the paths. Decoding means is adapted to generate output bit signals in response to the input bit signals. Logic means determines the correct phase relationship between the input bit signals and the output bit signals. Switching means, responsive to the logic means, selects the data path from the register to produce the correct phase relationship between the input bit signals and the output bit signals.
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