| 摘要 |
PURPOSE:To form a power MOS FET having a high withstand voltage and moreover enabled to reduce ON resistance by a method wherein resistivity of the surface layer of the circumferential part of a substrate is made higher than the central part to act as an active region. CONSTITUTION:To the surface of a high resistivity n type Si substrate 1 formed with an n<+> type diffusion layer 2 on another main surface of the substrate, reversely conductive type impurity ions B are implanted at extremely low concentration to the surface of the circumferential part of the substrate to be diffused using an SiO2 film 14 as a mask, and a more high resistivity layer 13 is formed. Then p type wells are diffused through a mask formed by etching and removing a part of an SiO2 film 15, and p type layers 3, 6, 7 are formed. A shallow p type diffusion layer 3a to act as a channel part is formed around the p type well layer 3. After then, the SiO2 film at the central part is etched to be removed, and a thin gate SiO2 film 16 is formed according to thermal oxidation. Then Si is deposited to form poly-Si layers 5, 5a, photoetching is performed to form a part thereof as a gate, and after then, an n<+> type source 4 is formed by selfalignment under the gate SiO2 film using the poly-Si layers 5, 5a as masks. The poly-Si layer 5a at the central part of the p type layer 3 is removed thereafter. |
