| 摘要 |
PURPOSE:To reduce resistances of electric power source lines and clock wirings, and to obtain a high speed large storage capacity semiconductor memory device by a method wherein two metal main wiring layers are connected by an impurity diffusion region or a polycrystalline silicon layer containing impurities extending in an array region both the two sides directional chip peripheral region along the array region. CONSTITUTION:At the whole of the side of a memory cell array part arranged with no peripheral circuit, inner circumferential earthing conductors 41, 52 and outer circumferential earthing conductors 42, 53 are connected by an impurity diffusion layer or a polycrystalline silicon layer 51. A group of clock wirings are arranged in the region C. Moreover, bonding pads 44, 45 and a contact opening parts array 54 are provided. An electric power source line 43 forms a loop type, and resistance thereof is suppressed to 1/2 of the usual example even when the same wiring width is used. This condition is extremely effective in regard to a current potential drop to be generated when a current, especially an instantaneous current is large like the high speed large storage capacity semiconductor memory device. Moreover, resistance of the clock wiring is also small to prevent the device from erroneous operation, and high speed operation also can be attained. |
