发明名称 METHOD FOR CONTROLLING TIME DIVISION DIGITAL EXCHANGE
摘要 PURPOSE:To utilize a channel specifying circuit during an idle channel period by detecting the idle channel in case of sending a signal to an extension circuit or a trunk circuit or specifying an SD/SCN address to detect the status of these circuits. CONSTITUTION:If the output of an AND circuit 21 is logical ''0'' at the specification of a channel, the output of a counter 13 is outputted from a multiplexer 22 and an AND circuit 21 detects the idle channel. When the output is logical ''1'', the output of an address specifying register 15 is outputted from the multiplexer 22. The output EMPCH of the AND circuit 21 indicating the idle channel is supplied to a CPU9 as an interruption signal and the CPU9 inputs the EMPCH signal and sends SD/SCN information. On the other hand, the output of the multiplexer 22 is supplied to a channel/address specifying circuit 23 and developed by a synchronizing signal generating decoder 23A and a package specification signal generating decoder 23B to form 19 kinds of signals SYNC0- SYNC7, SC0-SC2, PS0-PS7, etc.
申请公布号 JPS5979698(A) 申请公布日期 1984.05.08
申请号 JP19820189933 申请日期 1982.10.28
申请人 HASEGAWA DENKI SEISAKUSHO:KK;ANRITSU DENKI KK;MEISEI DENKI KK;NAKAYO TSUUSHINKI:KK;TAKAMISAWA DENKI SEISAKUSHO:KK;TAIKOU DENKI SEISAKUSHO:KK 发明人 TANAKA SHINGO;SATOU MITSUO;KUBO JIYUICHI;OOUCHI KAZUYUKI;KUSANAGI KOUICHI;GOTOU HIYOSHI
分类号 H04Q11/04;(IPC1-7):04Q11/04 主分类号 H04Q11/04
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