| 摘要 |
PURPOSE:To switch a buffer at a high speed without increasing a load of a CPU, by duplicating an address register and a length counter, and switching them successively. CONSTITUTION:In a direct memory access controller DMAC 16, a switching part 23 connects channels CH 1(21) to an address bus 9 in its initial state. Accordingly, the first data sent to a memory 2 from a I/O 4 is stored in an address set to address registers ADR 1(17). When the storage is ended, a numerical value ''1'' is added to the ADR 1, ''1'' is subtracted from length counters LCT 1(19), and the second data is stored in the following address of the memory 2 from the I/O 4. In this way, contents of the LCT 1 become ''0'', a switching signal is outputted, and the switching part 23 connects ADRs 2(18) to the bus 9. Accordingly, a data sent to the memory 2 from the I/O in the next time is stored in an address set to the ADRs 2(18). |
