发明名称 BIPOLAR RAM
摘要 PURPOSE:To extend the operating margin and to attain high speed operation, by providing a charge sweeper including a constant current source DELTAIst and a thyristor element flowing a current formed selectively at the constant current source according to a voltage level of a holding current line to the holding current line. CONSTITUTION:When a word line W0 is not selected and a word line Wn is switched into the selecting state, a drive TRQ7 is turned off and a Q8 is turned on, the potential V of the word line W0 is going to fall with the constant current source DELTAI, the current DELTAIst through TRs Q1, Q2 of the thyristor mode to be turned on and the holding current at the Ist flowing to the holding current line STO. In this case, the rise of the potential V of the line Wn is done in high speed with a large current from the TRQ8 and before the potential V of the lead W0 falls down, both the potentials are inverted. Since the turn-off time is slow, at least the current DELTAIst keeps flowing during the delay time through the said TRs Q1, Q2. Thus, the potential V of the word line W0 not selected is fallen down in high speed. As a result, the operation is quickened.
申请公布号 JPS5952491(A) 申请公布日期 1984.03.27
申请号 JP19820160996 申请日期 1982.09.17
申请人 HITACHI SEISAKUSHO KK 发明人 NAKANO TETSUO;KATOU YUKIO;YAMAGUCHI KUNIHIKO
分类号 G11C11/414;G11C11/34;(IPC1-7):11C11/34 主分类号 G11C11/414
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