| 摘要 |
PURPOSE:To shorten remarkably the number of machine cycles, by placing a two-input adder in parallel with a three-input adder, and suppressing an output of this two-input adder to zero so that it can be inputted instead of the first input among three inputs. CONSTITUTION:Each input information held by input registers 51, 52 passes through data buses 25, 26, respectively, is added by a two-input adder 72, and its output passes through a data bus 30, and is inputted to a switch 41. Zero suppression information by which low-order three bits of data of the data bus 30 are set to zero forcibly is selected, and is held by an input register 51 in the following cycle. In this case, the second input register 52 is reset. The contents of the input registers 51-53 are passed through the data buses 25-27 as operating information, are inputted to a three-input adder 71 and are added, and its output is held by an address register 61 through a data bus 31. |
