| 摘要 |
PURPOSE:To improve the layout efficiency of a semiconductor memory device by composing cell plate and bit lines of a polycrystaline silicon layer, a high melting point metal and metal silicide and the like. CONSTITUTION:A memory cell is formed by interposing a dielectric film 7 for a storage capacitor between a capacitor electrode 5 of a polycrystalline silicon layer and a cell plate and bit line 9A. A gold layer electrode and wiring layer 13 is formed via an insulating layer 11 on the memory cell. In this manner, the metal electrode and wiring layer is used as wirings or bonding pad which do not relate directly to the memory cell itself, and is effective for the reduction in the size of the memory chip and in the wiring length of the bit line. |
