发明名称 CLOCK PROCESSING DEVICE
摘要 <p>PURPOSE:To reduce a load of a main computer, and also to eliminate a delay of clock processing due to an overload state of a main computer, by executing the clock processing of the main computer by a microcomputer. CONSTITUTION:When a time updating part 42 is started by a clock signal of a microcomputer (mucpu) 4, it is outputted to a main computer (main CPU) 2 through a time generating part 43 and an interface (IF) 3 at every constant interval of time. When the time updating part 42 starts a processing part 44 at every constant interval of time, a processing discriminating data 46 and a target value 47 are stored in a data table 45 through the IF 3 and an input part 41 from the main CPU 2, therefore, the processing part 44 compares the target value with the present value in accordance with this discriminating data, and in case of coincidence, interruption is given to the main CPU 2, and coinciding discriminating data is outputted to the main CPU 2. The main CPU 2 operates a program by its interruption and the data. When the target value does not coincide with the present value, the processing part 44 updates the present value and stores it in an area 48.</p>
申请公布号 JPS592119(A) 申请公布日期 1984.01.07
申请号 JP19820112306 申请日期 1982.06.29
申请人 MEIDENSHA KK 发明人 WATANABE SHIGEO
分类号 G04F5/00;G06F1/00;G06F1/14 主分类号 G04F5/00
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