COMPUTER INTERFACE

摘要

"IMPROVEMENTS IN OR RELATING TO COMPUTERS" The disclosure relates to a computer having master control unit (MCU) interposed between a main memory (M) and the processor (CPU) whereby the address and data buses (ABUS and DBUS)from the (CPU) connected to the (MCU) which via secondary address and data bus (ABUS 2 and DBUS 2) is connected to the main memory (M). Control signals for reading and writing from the (CPU) are connected to the (MCU). The (MCU) issues its own secondary read and write signals (R2 and W2) when reading and writing in the main memory. The (MCU) contains an internal memory for a data descriptor table (DT) a set of internal index registers (XRO-XRQ), three arithmetic circuits (AC1-AC3), a mode decoder (MD), and index register decoder (XDEC), a mask and shift unit (MSU) and a range check and conversion unit (RCU). The virtual address issued by the CPU on the address bus (ABVS) consists of two parts the first part being used to indicate one of the possible entries in the data descriptor table (DT) required for translation of virtual addresses issued by the (CPU) on the address bus (ABUS) into real addresses issued by the (MCU)to the main memory on the secondary address bus (ABUS 2)and a second part containing a mode indicator to permit modification of the logic performed by the (MCU) when performing an address translation.The data descriptor table contains at least one entry for every addressable data element or structure in the main memory (M), whereby the actual entry is indicated by means of an address decoder (ADEC 1). The arrangement is such that the processor issues virtual addresses and the master controller converts the virtual addresses into real addresses in the main memory, the master control having means for performing any address calculation or index multiplication independent of any program functions.