| 摘要 |
PURPOSE:To collate an identification code having many bits especially by the minimum circuit scale, by collating identification code of input information in a series code as it is without expanding the input information to a parallel code. CONSTITUTION:Fixed parallel identification codes generated from an m-bit identification code generating circuit 5 are converted into series codes from the k-th bit of the information signal as the identification codes ID1-IDm for response information by a parallel-to-series converting circuit 9 controlled by a timing pulse generating circuit 7. The series identification codes ID1-IDm and input information (c) are applied to an EXO 6a and the output of the EXO 6a is stored by an FF 6c. An FF 6d is initialized by an output signal (f) from a timing pulse generating circuit 7 and the output terminal of the FF 6c is connected to the set input terminal S of the FF 6d. Consequently, the output signal of the FF 6d is inverted in polarity when the inconsistency of the identification code is detected. The output signal of the FF 6d is applied and stored to/in the terminal T of an FF 8 by a timing pulse (e). Thus, a collated result is obtained from a terminal 10. |
