| 摘要 |
PURPOSE:To eliminate the need for a master processor for schedule control, by allowing an optional processor to cause an interruption directly to another processor unit and have a communication with it. CONSTITUTION:A CPU10 is connected through an internal bus 20 to an I/O device 11, local memory 12, decoder 13 for specifying a shared memory CM, decoder 14 for starting an interruption, decoder 15 for an interruption destination data storage instruction, register 16 for storing interruption destination data, decoder 17 for interruption information input, bus buffer 18 for output information storage, and register 19 for input information storage respectively. Then the arbiter 21 for use control of a system bus SB has two input terminals BPRN and RQ and two output terminals BPRO and ANS. |
