发明名称 PHASE SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To make a narrow-band PLL instantaneously lock-in by passing the output of an oscillator through a delay element having a plural number of taps and comparing the phases of the output of taps with input signals to select the output of taps. CONSTITUTION:An output signal 1 is supplied to one sides of input terminals of phase comparators 17-1-17-N. The output 19-1 of a voltage variable oscillator 2 is successively supplied to delay elements 18-1-18-N, and the outputs 19-1 and 19-2-19-N of elements 18-1-18-N are supplied to the other sides of input terminals of the comparators 17-1-17-N. When the output of an adjacnet phase comparator is compared by means of voltage comparators 20-1-20-N-1, the code of the output is reversed to zero from one with a phase difference pi. The reversed comparator is detected by a detector 21 for detecting changing points, and an output signal 22 of log2N bits (N: natural number >=2) is sent to an output selector 23. The selector 23 outputs 24 a signal of phase difference pi by reversing it. As a result, a simply constructed, stabilized and narrow-band PLL can be locked in instantaneously to an input signal.
申请公布号 JPS58197923(A) 申请公布日期 1983.11.17
申请号 JP19820080228 申请日期 1982.05.14
申请人 HITACHI DENSHI KK 发明人 TAKESHITA KAZUYUKI;HIRANO YASUHIRO
分类号 H03L7/085;H03K5/26;H03L7/081;H04L7/033 主分类号 H03L7/085
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