| 摘要 |
PURPOSE:To reduce the number of inspecting bits, and to execute encoding and decoding at a high speed, by generating an error bit position designating signal from a syndrome, and also executing 1 bit error correction, 2 bit error detection and single bit byte error detection. CONSTITUTION:By taking OR of syndromes S0, S11...S5, generation of an error is detected. Also, by taking AND to be operated by OR of the syndromes S0, S1...S5, and inversion of exclusive OR, generation of a correction impossible error is detected. Furthermore, when the syndromes S0, S1...S5 are made to pass through a weight 5 detecting circuit 31 and logic gates 32, 33, generation of the correction impossible error is likewise detetected. In this state, from the syndrome, an error bit position designating signal is sent out, and when byte length and the number of inspecting bits are denoted by (b) and (r), respectively, 1 bit error correcting, 2 bit error detecting and single byte error detecting codes are constituted to optional (b) and (r) and to provide the code length to be (b+2) b2r-b-2. |
