| 摘要 |
<p>PURPOSE:To improve the reliability of the titled device, by making an arrangement that, when writing is made in an element to which writing can be made of a line decoder circuit for an auxiliary memory, the output of an address buffer circuit which corresponds to signals other than a prescribed address signal can be controlled at a high impedance. CONSTITUTION:In a storage device having an auxiliary memory cell 2 which acts as a redundancy bit for relieving faulty bits in addition to a main body memory cell 1, a terminal 13 which is to be used for selectively impressing a control signal Q upon line address buffers 11 and 12 is added and it is set that the output of the line address buffer upon which the control signal is impressed from the terminal 13 becomes a high-impedance condition. Therefore, fuses to be blown out in the 2nd line decoder circuit 4 which selects the auxiliary memory cell can successively be blown out separately and surely, the writing electric current can be minimized, and the cutting of the write signal line can be prevented.</p> |
