| 摘要 |
PURPOSE:To simplify and reduce the layout pattern of a writing circuit by commonly connecting the collector of a transistor in a bipolar type field programmable logic array (FPLA) and commonly using a collector load resistor. CONSTITUTION:In a decoder having n pieces of inverters of low selecting level, a Darlington transitor 1 for a driver circuit, a previous stage transistor Q2 and mXn diode matrix 8 are provided, and n pieces of output lines are inputted to a transistor Q. Numeral 3 designates a common collector region 3 of the tansistor Q, and n pieces of transistors Q are arranged in the region 3. The collectors of the transistors Q are commonly connected via wirings 7 and common collector region, are connected to a resistor 6 and to Vccp. Accordingly, (n-1) pieces of resistors Rc can be omitted. |
