IMPROVEMENT IN AND RELATING TO THE MANUFACTURE OF WAFER SCALE INTEGRATED CIRCUITS

摘要

The metallisation pattern for a wafer scale integrated circuit is achieved by the etching of a single metal layer (14) whereover photresist (16) has been exposed and developed using a step-and-repeat mask (18) for component bearing areas on the circuit (24) and a whole wafer reticle mask (26) for the areas of interconnection (30) between the component bearing areas (24).