| 摘要 |
In order to extract from a digital signal a train of sync pulses faithfully reproducing any phase jitter to which that signal is subjected, a pulse generator with a cadence equal to the reciprocal of the mean bit period is interrupted and restarted by a pulse shaper such as a monoflop in response to each incoming "1" bit. The pulse generator may comprise a second monoflop, triggerable by the first monoflop and provided with a feedback loop including a third monoflop which is inhibited by the first one in the presence of a "1" bit, or a free-running oscillator working into a frequency divider in the form of a pulse counter which is reset by the pulse shaper while the latter inhibits the oscillator.
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