| 摘要 |
A frequency oscillator for generating a square wave output pulse train is connected via a frequency divider circuit to a binary shift register which is designed as a divide-by-n counter with m counter stages, wherein m=n/2. Each stage is associated with an output. A resistor network is composed of m rated resistors each of which resistors is connected to a respective register output and in common to an input of a low-pass filter network forming the output circuit. The rating of the resistors is such that an k-th resistor associated with the k-th output of the shift register has the value <IMAGE> wherein R is a reference resistance value; k is a positive integer from 1 through m; C is 1/2 if m is an odd number; and C is 0 if m is an even number. Sine wave forms of different frequencies may be selectively chosen if the frequency divider circuit is provided with parallel inputs which are associated with different dividing ratios and are selectively coupled to the input of the binary shift register.
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