| 发明名称 |
METHOD OF PRODUCING INTEGRATED CIRCUIT |
| 摘要 |
In a fabrication sequence for VLSI MOS devices, an advantageous alignment mark for a wafer to be directly processed by electron beam lithography is made of tantalum disilicide protected by a silicon nitride layer. |
| 申请公布号 |
JPS58128(A) |
申请公布日期 |
1983.01.05 |
| 申请号 |
JP19820099424 |
申请日期 |
1982.06.11 |
| 申请人 |
WESTERN ELECTRIC CO INC |
发明人 |
DEIBUITSUDO BURUUSU FUREIZAA;RODERITSUKU KENTO WATSUTSU |
| 分类号 |
H01L21/027;G03F9/00;H01J37/304;H01L23/544 |
主分类号 |
H01L21/027 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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