| 摘要 |
PURPOSE:To increase a firing synchronization signal range by obtaining a firing signal of a thyristor from an OR circuit which receives an interline voltage of one phase and other interline voltage nor relative to this interline voltage. CONSTITUTION:Anti-parallel connection thyristors 1-6 are provided between 3- phase AC power sources VR, VS, VT and a load 7. NOT circuits 8, 9, 10 which obtain interline voltages VRS, VST, VTR are provided, and firing synchronization signals S10-S60 are respectively obtained from OR circuits 11-16 which receives the outputs of the NOT circuits 8, 9, 10, the voltages VSR, VTS, VTR, an interline voltage of one phase, and other interline voltage not relative to the interline voltage. In this manner, the firing synchronization signal of the respective thyristors can be delayed as compared with the conventional ones, and a power source voltage can be applies to a load as it is even at a high power factor loading time. |
