发明名称 Circuit arrangement for time division multiplex telecommunications switching systems, in particular PCM telephone switching systems, with a multi-stage switching network
摘要 A switching network comprising a first time division multiplex stage (Z11 to Z14), a space division multiplex stage (R1, R2, R3,...) and a final time division multiplex stage (Z31 to Z34) in each case has one demultiplexer (e.g. V11 to V14) for each time division multiplexer (e.g. Z11) downstream of the first time division multiplex stage (Z11 to Z14), and in each case one multiplexer (e.g. V61 to V64) for each time division multiplexer (e.g. Z32) upstream of the final time division multiplex stage (Z31 to Z34). The plurality of intermediate time division multiplex lines (e.g. X1) in each case emerging from one time division multiplexer (e.g. Z11) of the first stage (Z11 to Z14) and the plurality of intermediate time division multiplex lines (e.g. Y2) in each case leading to a time division multiplexer (e.g. Z32) of the final stage (Z31 to Z34) are connected to the same space division multiplexer (R) of the middle switching stage (R1, R2, R3,...). The joint action of the demultiplexers (V11 to V14, V21 to V24, V31 to V34, V41 to V44) and multiplexers (V51 to V54, V61 to V64, V71 to V74, V81 to V84) creates the possibility of a time slot change in the space stage (R1, R2, R3,...) in terms of the time slots selected in each case in the first stage (Z11 to Z14) and in the final stage (Z31 to Z34). <IMAGE>
申请公布号 DE3110825(A1) 申请公布日期 1982.09.30
申请号 DE19813110825 申请日期 1981.03.19
申请人 SIEMENS AG 发明人 NEUFANG,KARLHEINZ
分类号 H04Q11/06;(IPC1-7):H04Q11/04 主分类号 H04Q11/06
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