| 摘要 |
PURPOSE:To compensate the phase of a sampling pulse automatically by phase- comparing an output obtained by dividing in frequency and delaying an original clock pulse with the standard signal of a data sampling and controlling a divider by the compared output. CONSTITUTION:An original clock pulse is divided by a divider consisting of FFs 60, 63, 65 and exclusive ''or'' circuits 62, 64, 66 and delayed to plural different time by a delay device 67. A data selector 68 selects any one of delay outputs, a phase detector 55 phase-compares the selected output with a clock run IN signal 53 to obtain phase error voltage. A comparator 58 compares the phase error voltage with the standard voltage 59 to output a positive or negative control signal. The positive or negative control signal makes an up/down counter 54 count up or down. Then the lower bit of the counter controls the data selection of a data selector 68 and the upper bit controls the divider. |
