| 摘要 |
PURPOSE:To allow to increase no gate retardation time even when the number of fan out is increased for the subject gate array by a method wherein the gate array is constituted of a plurality of C-MOS transistors of reference size and a plurality of C-MOS transistors of the size multiplied by the natural numbers which are aligned on the same Si substrate. CONSTITUTION:A plurality of reference sized C-MOS transistors 11, a plurality of double-sized C-MOS transistors 12, and a plurality of threefold-sized C-MOS transistors 13 are provided on the Si substrate 10, and the substrate 10 for one chip component as above is formed by connecting it to all directions. At this point, the double-size above-mentioned means the area ratio of the transistors. Then, in order to form the inverter gate of the fan out number 2, inverter gates 14 and 15 are arranged, and they are connected in the final masking process using a metal 16. Accordingly, even when the transistors of large charging output are combined and the fan out number is increased, the gate retardation time remains unchanged when compared with that of the fan out number 1. |
