发明名称 INPUT/OUTPUT INTERFACE DEVICE
摘要 <p>PURPOSE:To obtain an input/output interface device having optional bit length, and also to economically repair it when it is faulty, by connecting plural output unit elements and input unit elements in cascade. CONSTITUTION:Connection of mutual unit elements is executed between a series data input terminal SDin and a series data output terminal SDout, between a clock signal input terminal CLin and a clock signal output terminal CLout, and between a selective strobe signal input terminal SBin and a selective strobe signal output terminal SBout. A data line lD and a clock line lO are connected in series, a data line DL and a clock line are formed, and they are connected to a numerical controller NC. A signal which has been brought to serial-parallel conversion and also logical level-high level conversion is fetched from a parallel data output terminal PDout of output unit elements SPU1, SPU2, and for instance, is used for an on-and-off control signal of the main shaft.</p>
申请公布号 JPS57139854(A) 申请公布日期 1982.08.30
申请号 JP19810025957 申请日期 1981.02.24
申请人 FUJITSU FANUC KK 发明人 KOMIYA HIDETSUGU;INOUE MICHIYA
分类号 H03M9/00;G06F1/18;G06F13/00;G06F13/38;G06F13/42 主分类号 H03M9/00
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