| 摘要 |
<p>PURPOSE:To decrease the number of circuits required for fine adjustment, by varying the width of modified FM (MFM) readout pulse via a delay circuit and adjusting the relative time relation with an NRZ data forming clock having double period of a PLL output signal. CONSTITUTION:A D type FF301 is set with a read-out MFM signal, a set output is delayed at a delay circuit 300 and different delay outputs are generated sequentially. An FF301 is reset with a delay output via NAND gates A-C to be selected, the width of MFM readout pulse is varied and the pulse with desired width can be selected. The NRZ data can be detected through phase comparison with a PLL consisting of a phase-voltage conversion circuit 303, LPF304 and voltage controlled oscillator 305. On the other hand, an NRZ signal forming clock with double period as the period of a feedback output of the PLL is generated from this oscillator 305, the relative time relation with the MFM readout signal can be adjusted automatically, and the number of circuits required for fine adjustment is less and a data conversion circuit with ease of adjustment can be achieved.</p> |
