| 摘要 |
An EFL D-type latch employing an EFL storage cell (17) controlled by a two-level tree of differential transistor pairs (12, 14 and 32, 34). Also described are counter cells, up counters, down counters and up/down counters, including binary, hexadecimal and BCD types, which can be formed from master/slave combinations of D-type and D-type latches. Examples of specific three-level and four-level EFL realizations of the counter cells are also described. |
