| 摘要 |
PURPOSE:To input a clock to be inputted optionally and independently, by providing a diagnostic switching mode input pin for a unit circuit and a clock pin for a test. CONSTITUTION:An operation clock P-CL operating a unit circuit 1 is distributed by a clock selecting circuit 2, and phase clocks A1-A30 are distributed by clock distributing circuits C1-C6 to output signals B1-Bn. When the circuit 1 requires an optionally independent clock, logic ''1'' is outputted to a diagnostic switching mode input terminal S1, and logic ''0'' to an S2 from external devices respectively. Consequently, logic signal of test clocks T1-T5 are inputted to one-side input terminals of gates to which the phase clocks A1-A30 should be outputted. When logical circuits constituting the circuit 1 require clocks at the same time, the terminal S1 is supplied with ''0'' and the S2 is supplied with ''1''. Consequently, the logical circuits are connected to the gates to which in-phase clocks A1-A5 should be outputted. |
