发明名称 FAILURE CHECK SYSTEM
摘要 PURPOSE:To enable failure analysis quickly at the detection of a failure, by storing all the prescribed amount of recent information received and transmitted between a processor and a device to be controlled and using the information for the analysis of the failure through readout at the detection of the failure. CONSTITUTION:An information storage circuit TRM stores all the information received and transmitted between a processor CPU and a storage device MEM or device to be controlled for a prescribed number of words W. When a failure detection circuit ILD detects failed information, a failure detection signal EM is given to the CPU and the TRM to store the recent information of W words stored up to now. On the other hand, the CPU executes a failure analysis program, analyzes a program status data PSW and knows the execution address of a data area DA. Next, the information stored in the information storage circuit TRM is analyzed and recognizes that the said execution address is based on the address value stored in an index register.
申请公布号 JPS5755462(A) 申请公布日期 1982.04.02
申请号 JP19800131269 申请日期 1980.09.20
申请人 FUJITSU KK 发明人 NAGATA TAKASHI
分类号 G06F11/34;G06F11/07 主分类号 G06F11/34
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