发明名称 ERROR PROCESSING SYSTEM
摘要 PURPOSE:To prevent the adverse effect based on the consecutive occurrences of errors, by neglecting errors less than the same class produced succeedingly, until the processing of instruction and the first error processing are finished. CONSTITUTION:During the execution of a job 1, if an error of class (1) takes place, this is detected with one of an error detecting circuit 3-0-3-2 and outputted from an OR circuit 8. When the output of the OR circuit 8 is applied to a set terminal of an error mask flag latch 11, this latch 11 is set and outputted to an AND circuit 14 to turn off the AND circuit 14. Thus, based on the error of the class (1), even if the error of the class (1) is in existence even with the next instruction processing stage and the detecting signal is transmitted to the OR circuit 8, this is not reported because the AND circuit 14 is in off-state.
申请公布号 JPS5730039(A) 申请公布日期 1982.02.18
申请号 JP19800104587 申请日期 1980.07.30
申请人 FUJITSU LTD 发明人 IYOTA HIDEO;OOKAWA MASAYUKI
分类号 G06F9/38;G06F11/00 主分类号 G06F9/38
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