| 摘要 |
Apparatus for synchronizing the bit clock in a digital receiver to be in phase with bits of a received data stream, utilizes a frequency source locked to a system-wide frequency and frequency-arithmetic means for providing first and second local frequencies respectively slightly greater and slightly less than a multiple of the system-wide frequency. Countdown circuitry provides a multiplicity of local clock phases at the local clock frequency for phase comparison with the clock frequency derived from the received data stream and for subsequent digital phase adjustment to cause the local baud clock to track the received data stream bit transition frequency.
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