发明名称 MEMORY CONTROL SYSTEM
摘要 PURPOSE:To obtain a normal data even though an error exists in both words of a doubled memory, by dividing each word within two memories into plural subgroups and then giving a check to the data with every subgroup. CONSTITUTION:No error exists at the byte position i (i=0-3) of a temporary register 3, and an error exists at the byte position i of a register 3'. In such case, a gate Gi opens by the data effective signal Si sent from a parity check circuit PCi, and a gate G'i is closed since the signal S'i of a parity check circuit PC'i is off. As a result, the output of Gi, i.e., a normal data is set at the byte position i of a reading register 5. In this case, the error detection signal ei of the circuit PCi is off. Thus an AND gate Gei is closed to deliver no error signal E to the system. The system has no breakdown as long as the position of the faulty subgroup differs and even though a fault exists in both doubled memories.
申请公布号 JPS56163596(A) 申请公布日期 1981.12.16
申请号 JP19800064835 申请日期 1980.05.16
申请人 FUJITSU LTD 发明人 KUSUMOTO KOUJI
分类号 G06F12/16;G06F11/10 主分类号 G06F12/16
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