发明名称 DIGITAL TYPE FREQUENCY DISCRIMINATOR
摘要 PURPOSE:To expand an initial value set range by corresponding the output of the low-order bits of a binary counter forming a discriminator to a discrimination range. CONSTITUTION:A binary counter 6 of an m bits which counts the clock pulses existing in the period of 1/K of input signals (the pulses to be measured) and stops counting when it counts prescribed value Nm is provided. The low-order n bits of this counter 6 are used as a deviation so that the center value of said deviation is made 2<n-1> and that a deviation output of maximum 2<n-1> is obtained. The initial value Np at the start of counting of the counter 6 is set by the equation-1. Here, K is real number of <=1, fCK is clock pulse frequency, fR is input signal frequency, Nm is positive integer, and L is positive integer including 0. Then, the maximum value that the initial value Np can take is 2<m>-2<n>, and the preset value of a wide range is taken.
申请公布号 JPS56158959(A) 申请公布日期 1981.12.08
申请号 JP19800063600 申请日期 1980.05.13
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 CHIYUUNO MASARU;WADA TATSUO;GOTOU YASUHIRO;YAMAGUCHI SEIJI;OOTA YUTAKA;YABU TOSHIOMI
分类号 G01R23/10;G01R23/15 主分类号 G01R23/10
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