发明名称 MULTIPLE REGISTER BLOCK CONTROLLER
摘要 PURPOSE:To increase execution speed of a program by suppressing the frequency of data transfer between a main storage device and register blocks in a computer system. CONSTITUTION:Data transfer control part 12 is informed of the generation of interruption via line 15 to perform prescribed processing. In the restart of a program after the interruption, control part 12 reads the contents of block RB in register block group 1 having a number, given to line 13, from save region S in corresponding main storage device 2 and returns it to corresponding block RB, and at the same time, the contents of save indicating register SLR3 are decreased by one via line 4. Every time the contents of block-number specifying register ALR7 are decreased, whether the contents of RB to be used next are saved in region S or not is inverstigated by referring to SLR3 and when so, data in corresponding region S is listed in RB while the contents of SLR3 are decreased by one.
申请公布号 JPS56148779(A) 申请公布日期 1981.11.18
申请号 JP19800050633 申请日期 1980.04.17
申请人 MITSUBISHI ELECTRIC CORP 发明人 UEDA HISAZUMI
分类号 G06F9/46;G06F9/48 主分类号 G06F9/46
代理机构 代理人
主权项
地址