| 摘要 |
A testing circuit 30 is provided for a semiconductor device having a test mode in which the information about built-in memory cannot be read after testing and cutting a pad formed in a scribe area. The scribe pad 1 and the scribe ROM 2 are formed in the cutting area b of a wafer. Upon power-up of a chip a, a power-on reset circuit 4 transmits a reset signal to a mode register 10. After setting the initial resister value to "00", a mode switch signal is input from the mode switch terminal, the scribe ROM 2 is activated, and the test mode is set. In this process, a Manchester-coded signal is provided from the scribe PAD 1, decoded by a frequency-divided clock provided from a clock dividing circuit 8, the value of the register in the test mode in the mode register 10 is set, and external reset is asserted or negated. Once the wafer is diced the ROM for transition to the test mode is annihilated.
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