SEMICONDUCTOR DEVICE AND METHOD FOR ACCURATE CLOCK DOMAIN SYNCHRONIZATION OVER A WIDE FREQUENCY RANGE

摘要

A clock synchronization circuit has a clock synchronization detector. A first variable delay circuit is connected to a first input unit of the clock synchronization detector. A controller is connected to a digital output unit of the clock synchronization detector and a control input unit of the first variable delay circuit. A first clock signal is connected to the first variable delay circuit. A second clock signal is connected to a second input unit of the clock synchronization detector. The clock synchronization detector includes a first flip-flop and a first delay element. The first delay element is connected between the first variable delay circuit and a data input unit of the first flip-flop. A second variable delay circuit is connected to a second input unit of the clock synchronization detector. A multiplexer is connected between the first variable delay circuit and the first input unit of the clock synchronization detector. An offset compensation unit calibrates the clock synchronization detector. The clock synchronization circuit can perform accurate clock-phase detection over a wide frequency range.