| 摘要 |
PURPOSE:To decrease the number of times of using a timer without lowering the easiness of changing a timer set value, by receiving plural time count starting signals, generating a preset value signal by the logical circuit, and presetting by this preset value signal, in case when an S/W presettable timer is used in the sequence circuit. CONSTITUTION:When a timer start request signal from the sequence logical part 11 is inputted to the logical circuit 10 part in the sequence logical circuit 1, a start signal 34 of the timer 24 is outputted. And, after a delay time, when a time count-up signal 44 is inputted to the circuit 10 from the timer, a start signal 30 is outputted. In this case, a time count value which is used in the logical part 11 is selected, and it is set as a preset value 50. After counting the S/W set time from in the circuit 10, a time count-up signal 40 is input, the signal 40 is outputted to the logical part 11, the timer start request signal drops, and the sequence goes forward. |
