发明名称 DELAY CIRCUIT OF VARIABLE LENGTH
摘要 <p>PURPOSE:To give a delay simply, to enable a circuit to be used an arrangement conversion circuit and to establish a circuit suitable for one chip circuit integration, by the selective switching of the connection which gives a delay for two inputs and outputs in series with two delay elements, for two delay elements of variable length having the terminal setting extent of delay. CONSTITUTION:Serial data is input to input terminals 1, 2 and binary code signal 13 to set the extent of delay for a delay element 8 of variable length is input to an input terminal 3. The binary code signal 13 is converted at a binary code conversion circuit 12, where a binary code signal 14 to set the extent of delay of a delay element 9 of variable length can be obtained. Further, the data input to the input terminals 1 and 2 is input to two input selection circuits 10, 11, and either one of them is selected and output with the selection signal input from an input terminal 5.</p>
申请公布号 JPS56120208(A) 申请公布日期 1981.09.21
申请号 JP19800023556 申请日期 1980.02.27
申请人 NIPPON ELECTRIC CO 发明人 KANEMASA AKIRA
分类号 G06F17/14;H03H11/26 主分类号 G06F17/14
代理机构 代理人
主权项
地址