| 摘要 |
PURPOSE:To reduce a capacitance between a signal input terminal and a source (drain) by a method wherein electrodes are taken separately out of a front gate and a back gate of a J-FET and the back gate is connected to a source or a drain. CONSTITUTION:Within an N type semiconductor layer 102, as if surrounding a part of this side face, a mosaic like P<+> type backage area 103, N type source areas 105a-105c, N type drain areas 106a-106d and a mosaic like front gate 108 are formed. Within the area 103, a P<+> type area 121 for the contact use is formed and at an adjacent prt thereof, an N<+> type contact area 120 is formed. At this time, a back gate drain electrode wiring 122 is in contact with areas 120 and 121 through a polysilicon film 114'. The electrode wiring 122 can be directly in contact with the areas 120 and 121, and at this time, a junction capacitance between a drain and a back gate becomes zero. And further, an input signal is entered in the front gate 108. |
