Multiprocessor system including I/O interrupt handling mechanism.

摘要

For increased flexibility and efficiency of handling I/O interrupt requests (I/O IR's) in a multiprocessor system having a system controller (SC, 22), processors (CP 20, 21) shared main storage (23) and in I/O processor (IOP in 24), the IOP inserts I/O IR entries onto the queues in MS in accordance with the type of interrupt which entries are only removed by the CPs, after their selection by the controller (SC) for execution of an appropriate interruption handling program. Bit positions in an I/O IR pending register (46) in the SC are respectively assigned to the I/O IR queues in MS, and their order determines queue priority for CP handling. An I/O IR sets a corresponding bit position in register (46) an controls the corresponding queue entry. A broadcast bus (11) connects the bit positions of the pending register to each of the CPs.