| 摘要 |
PURPOSE:To prevent the lock failure dependent upon disturbance, by providing the comparator of a low phase sensitivity and the comparator of a high phase sensitivity in parallel. CONSTITUTION:Input signal SL and signal SV' obtained by delaying the phase of reference signal SV out of the output of VCO11 by pi/2 are supplied to phase comparator 12A, and input signal SL and reference signal SV are supplied to phase and frequency comparator 12B. The phase sensitivity of phase comparator 12A is selected low comparatively, but the phase sensitivity of phase and frequency comparator 12B is selected very higher than that of comparator 12A. When the phase difference is smaller than the reefrence phase difference, only the pulse output of phase and frequency comparator 12B is obtained, but the pulse output is not input to charge pump 16. When the phase difference exceeds the reference phase difference, VCO11 is controlled mainly by the output of phase and frequency comparator 12B, and the response speed of PLL10 becomes rapid correspondingly to extension of the loop band width. |
