Error detection in microcomputer system - using detector logic coupled to programme memory to identify error in programme execution or memory

摘要

The system has a number of memory modules (11-14) coupled to the central processor (1) that contain the operating programme. A separate bank of memories (15-19) data. Outputs from the programme memories are coupled to a NAND gate (45) such that pulses are generated to a time base for each successful operation. A negator (46) is coupled to an LED indicator (47). Provided that the programme execution is proceeding correctly, the LED is active. In the event of a malfunction the LED is either inactive or flickers. A separate LED (51) is activated when a programme interrupt is in progress for communication with peripherals (2,3).