| 摘要 |
PURPOSE:To prevent the inconvenience that the time limit output is made regardless that no time limit trigger signal is fed, by providing the delay circuit holding the reset terminal of RS flip flop at H level for a given time immediately after the application of power supply. CONSTITUTION:The time limit trigger signal is input to the set terminal S of the RS flip flop F, the clock pulse of the oscillation section 1 is counted at the counter 2, and the output is input to the reset terminal R of the flip flop F. When RS both inputs are at H level, the lacth circuit 6 is provided so that the output Q' of the flip flop F can be held at L level, and the operation of the counter 2 is controlled via the control section 3 with the output of the flip flop F and the delay circuit 7 to hold the reset terminal R of the flip flop F for a given time after the application of power supply is provided. |
