| 摘要 |
PURPOSE:To obtain the frequency multiplication circuit in which accurate n-times frequency can be obtained, by compensating the value of the deciaml point or below of the measurement value of the period of input pulse. CONSTITUTION:The timing circuit 6 producing the set signal S and reset signal R at the leading of the input signal fi resets the 1/n frequency divider 7 and the up- counter 3 with the signal R. After that, the counter 3 counts the 1/n output of the output of the high frequency oscillator 1. The count value of the counter 3, e.g. D is set to the down-counter 5 via the register 9 with up-counter with the signal S from the circuit 6. This counter 5 produces output every time the output of the high frequency oscillator 1 is counted by D. The correction circuit 8 switches the set value to the down-counter 5 to D+1 according to the error component of the frequency divider 7 and controls the register 9 so that the output of the counter 5 can be output accurately by (n) pulses ar one period of the input signal fi. |
