| 摘要 |
PURPOSE:To enable reducing the size of a memory cell by forming bit lines formed of wirings of a lower layer in a zone connected with a memory cell on a memory cell array and an upper layer in a zone not connected with the cell. CONSTITUTION:Memory cells M connected with bit line B are gathered at sense amplifier SA side, and memory cells MC connected with bit line -B are gathered at the lower side. The first layer polycrystalline silicon P1 for forming one electrode of a capacitor, a diffused layer J for forming one bit line B connected with a sense amplifier AS, the contact C of the first wiring layer B1 with the diffused layer J, a substrate S, the second layer polycrystalline silicon W1 for forming a word line, an interlayer insulating film CV, the gate Q of a transistor, a capacitor CA, and the second layer wiring layer -B1 for forming the other bit wirings -B are provided. Thus, since the sets of the bit lines connected with the sense amplifier are superposed, there is no limit of the memory cells due to the bit lines to reduce the size of the memory cells. |
