发明名称 OVERLAPPING CIRCUIT FOR NEW AND OLD OUTPUT
摘要 PURPOSE:To prevent the failure signal output, by delaying the renewal of memory means for the time for overlapping and eliminating the uncertain output of the memory means accompanied with renewal. CONSTITUTION:The memory circuit 4 is renewed with the output of the delay circuit 11. By comparing the output of the circuit 4 with the input signals 1-1, 1-2, 2-1, 2-3 at the comparison circuit 10, the coincidence signal indicating the end of renewal of the circuit 4 is obtained as the output. This coincidence signal and the inverting delay signal inverting the output of the circuit 11 at the inversion circuit 11 are input to the gate circuit 14 to obtain the gate signal of the gate circuit 6. The output of the circuit 6 is input to the expansion circuit 8 for expansion, allowing to output the old state output 9-1 before the renewal of the circuit 4 and to obtain the new state output 9-4 after that. By tying the outputs of the circuits 7, 8, the old output 9-1 and the new output 9-4 are overlapped while the time corresponding to the delay time of the circuit 11. Before that, 9-1 only is output and after that, 9-4 only is output. Thus, the incorrect expansion signals 9-2, 9-3 accompanied with the renewal are not appeared as output.
申请公布号 JPS55142474(A) 申请公布日期 1980.11.07
申请号 JP19790051054 申请日期 1979.04.24
申请人 NIPPON ELECTRIC CO 发明人 FURUYA AKIO
分类号 G06F12/06;G06F12/00;G11C7/24 主分类号 G06F12/06
代理机构 代理人
主权项
地址