| 摘要 |
PURPOSE:To obtain a high-speed programmable logic array by connecting a part, at least, of ouput lines of the AND array to the second array through inverters respectively. CONSTITUTION:Inputs I1-Il are input to the first AND array A1, and AND array lines A1-Am are input to the second AND array A2 (A1'-Am') through inverters N1-Nm, and outputs O1'-On' becomes outputs O1-On through inverters. Therefore, the output becomes equivalent to the OR array practically, and the circuit can be handled similarly to the PLA of AND-OR constitution, and then, parasitic capacity CS to the substrate becomes very small even for one inverter, and delay of delay time tpd dependent upon capacity CS is improved considerably to eliminate almost irregularity of time tpd. |
