| 摘要 |
PURPOSE:To reduce the hardware without providing interface circuit, by synchronizing the clock of the microprocessor with the memory cycle of the path memory and controlling the write enable of path memory. CONSTITUTION:The path memory reads in the information of the rpimary highway 2 and that of the microprocessor 1, they are fed to the secondary highway 5, and the exchanging operation is made in time sharing by replacing the time slot with the highway 2 and the secondary highway 5 under the control of the processor 1. The exchanging communication path is provided with the memory control memory 13 designating to write-in either of the information on the highways 2 and 5 or the information from the processor 1 to the memory 6, the memory cycle of the memory 6 is divided into three, highway data write cycle, read cycle, and processor cycle, and the cycles are synchronized with the clock of the processor 1, enabling the processor 1 to directly write in and read out the memory 6. |
